1. Field of the Invention
The present invention relates to a memory controller, a memory control method, rate conversion apparatus, a rate conversion method, image-signal-processing apparatus, an image-signal-processing method and program for executing each of those methods.
More specifically, it relates to the memory controller and the like that are preferably applied when converting the number of pixels to another for a display.
2. Description of Related Art
As the flat panel display, liquid crystal display (LCD), plasma display (PDP) and the like have been well known. The fineness on the picture quality of these displays is determined depending on the quantities of pixels in the vertical and horizontal directions thereof. For example, there are standards such as XGA (768×1024 pixels), SXGA (1024×1280 pixels) and the like.
Further, as the image signal, 480i signal, 720p signal, 1080i signal and the like have been usually used. Here, these values indicate the number of lines, “i” indicates interlace type and “p” indicates progressive type. For example, the 480i signal has a resolution of 720×480 dots, the 720p signal has a resolution of 1024×720 dots and the 1080i signal has a resolution of 1920×1080 dots.
Conventionally, in the image display apparatus, the number of pixels has been converted to another in order to enable a part or all of input image signals to be displayed on its display. In this case, a rate conversion apparatus converts the quantities of pixels in the vertical and horizontal directions of the display.
The aforementioned rate conversion apparatus can be comprised of a first memory, for example, a frame memory, which is a burst transmission type large-capacity memory and a second memory, which is random access type dual port memory. In this apparatus, input image signals are stored in the first memory temporarily and the image signals are transferred from the first memory to the second memory successively in the unit of line and written therein. Then, the image signals are read out of the second memory at a pixel cycle and a line cycle of after-converted so as to obtain output image signals.
If such the transfer, however, is used, it is difficult to secure stable data transmission band between the first memory and the second memory. Such the transfer provides less use efficiency.
Further, in the rate conversion apparatus having the above configuration, write and read-out of the image signal to/of the first memory are carried out through the same data bus.
To secure stable data transmission band between the first memory and the second memory and raise the use efficiency in the rate conversion apparatus having the above configuration, it is conceivable that transmission of the image signals from the first memory to the second memory is carried out every specified time. In this case, the image signals are transferred from a write buffer to the first memory through the data bus based on a write request and written therein. The image signals are then transferred from the first memory to a read-out buffer through the data bus based on a read-out request every specified time. Finally, the image signals are transferred from this read-out buffer to the second memory.
This, however, depends on the write timing by the write request to perform the read-out based on an input of a read-out request every specified time.
Additionally, in the aforementioned rate conversion apparatus, for example, using a conversion objective pixel data string of the first image signal, a pixel data string of an effective pixel section in the horizontal direction of the second image signal is generated with keeping the same pixel data continuous at a rate corresponding to the magnification of the number of pixels.
For example, if an image-signal-processing unit for creating new pixel data corresponding to each pixel position of the effective pixel section in the horizontal direction of the second image signal is provided using a predetermined number of taps in the horizontal direction at a post stage of such the rate conversion apparatus, it is conceivable that this rate conversion apparatus builds up the predetermined number of the taps in the horizontal direction corresponding to each pixel position of the effective pixel section in the horizontal direction of the second image signal.
This, however, depends on the magnification of the number of pixels to obtain the predetermined number of the taps in the horizontal direction in the arrangement of the pixel data of the image signal (first image signal) before rate conversion. It is also depends on the magnification of the number of pixels that the output start delay until a predetermined number of the taps in the horizontal direction is outputted from a register since the pixel data string of an image signal after rate conversion is inputted to the shift register can be altered.
A first object of the present invention is to secure stable data transmission band between the first memory and the second memory and raise its use efficiency.
A second object of the present invention is to enable a read-out to be performed on the basis of an input of a read-out request every specified time without depending on the write timing by the write request.
A third object of the present invention is to obtain the predetermined number of the taps in the horizontal direction in the arrangement of the pixel data of the image signal (first image signal) before rate conversion without depending on the magnification of the number of pixels.
A fourth object of the present invention is that the output start delay until a predetermined number of the taps in the horizontal direction is outputted from the register since the pixel data string of an image signal after rate conversion is inputted to the shift register can be fixed at each line without depending upon the magnification of the number of pixels.